1. Technical Field of the Invention
The present invention relates to a semiconductor device including a capacitive element with an MIM structure.
2. Description of the Related Art
An RF (radio-frequency) analog device comprises active elements for handling high-frequency signals and passive elements such as resistive elements and capacitive elements. In RF analog devices, reduction of parasitic resistances and parasitic capacitances is demanded in view of improvement in high-speed operability and reduction in power consumption. Therefore, in capacitive elements, an MIM (Metal-Insulator-Metal) capacitive element is widely used in which parasitic resistances and parasitic capacitances are remarkably smaller than those of conventional MOS capacitive elements.
On the other hand, a structure in which such an RF analog device is installed inside a logic device and formed into one chip has also been developed. In order to realize such a structure, integration of the structures and manufacturing processes of these devices is required. In a logic device, in view of high-speed operability of the element and reduction in power consumption, a structure including multilayer copper interconnections is generally used. It is an important technical object how the structure or processes of the MIM capacitive elements are adapted to such a copper multilayer interconnection structure.
Herein, when the MIM capacitive element is applied to the copper multilayer interconnection structure, it is considered that a part of the copper interconnection is commonly used as an electrode of the MIM capacitive element. However, the copper interconnection is usually formed by a damascene process, so that it is difficult to satisfactorily obtain flatness of the surface due to dishing. This problem of dishing becomes conspicuous when a Cu layer with a wide surface area like an electrode part of the capacitive element is formed, and it is very difficult to form the electrode part of the MIM capacitive element by a Cu film.
On the other hand, Japanese Published Unexamined Patent Publication No. 2003-264235 discloses a semiconductor device in which a Cu interconnection structure is connected to the lower surface of a lower electrode of an MIM capacitive element and charges are supplied to the lower electrode via the Cu interconnection. The semiconductor device disclosed in this publication is shown in FIG. 1. As shown in FIG. 1, on the copper interconnections 34a through 34d, a TIN film 38, an SiO2 film 39, and a TIN film 40 are formed in order so as to have film thicknesses of 100 nm, 40 nm, and 150 nm, respectively, and the TiN film 38 is a lower electrode of the MIM.
However, the capacitive element disclosed in said publication has the following problems. First, since a structure in which the lower electrode of the capacitive element is layered on the copper interconnections via a barrier metal is provided, it is still difficult to obtain flatness of the lower electrode. Second, the barrier metal is normally made of a high-resistance material, so that the resistance of the lower electrode becomes high. It is considered that the resistance is lowered by increasing the film thickness, however, the barrier metal of TiN or the like is generally high in inner stress, and there is a limitation in the increase in film thickness. Third, the barrier metal is high in resistance and high in inner stress, so that an increase in area is difficult, and it is difficult to form a capacitive element with a large capacitance.
As described above, in the structure in which an MIM capacitive element is provided above the interconnections, the flatness of the lower electrode is degraded and the selection of the material of the lower electrode is restricted, and as a result, it becomes difficult to obtain a capacitive element with desired performance.